The Timer IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SOC or FPGA development. The Timer IIP can be implemented in any technology.

The Timer IIP core supports the standard protocol of Timer. It can also support a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

The Timer IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The Timer IIP is validated using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.