The eDP Receiver IIP Core is a full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The eDP Receiver IIP can be implemented in any technology.

The eDP Receiver IIP core supports the eDP 1.4b specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.

The eDP Receiver IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The eDP Receiver IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.