The USB1.1 Device IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The USB1.1 Device IIP can be implemented in any technology.

The USB1.1 Device IIP core supports the USB 1.1 Specification. It can also supports a variety of host bus interfaces for easy adoption into any design architecture – AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

The USB1.1 Device IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The USB1.1 Device IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.