The LIN IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SOC or FPGA development. The LIN IIP can be implemented in any technology.

The LIN IIP core is compliant with the LIN 2.2A. It can also supports a variety of host bus interfaces for easy adoption into any design architecture - AHB, APB, OCP, Wishbone, VCI, Avalon, PLB, Wishbone or custom buses.

The LIN IIP is delivered in Verilog RTL that can be implemented in an ASIC or FPGA. The LIN IIP is validated in using FPGA. The core includes RTL code, test scripts and a test environment for complete simulation.